Hi, What could be a simple sound format for Oberon, possibly something better to PC Speaker or ZX Spectrum buzzer. It should be very conservative on memory use. Did Ceres have some sound output? Many thanks. -- Tomas Kral <thomas.kral@email.cz>
Before discussing the audio format you need a sound HW. Jörg -----Original Message----- From: Oberon <oberon-bounces@lists.inf.ethz.ch> On Behalf Of Tomas Kral Sent: Monday, October 29, 2018 2:22 PM To: Oberon@lists.inf.ethz.ch Subject: [Oberon] FPGA - Oberon - Sound Hi, What could be a simple sound format for Oberon, possibly something better to PC Speaker or ZX Spectrum buzzer. It should be very conservative on memory use. Did Ceres have some sound output? Many thanks. -- Tomas Kral <thomas.kral@email.cz> -- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
Pepino can do sound :) Yamaha OPL2 chip emulated in Verilog: http://www.saanlima.com/videos/IMG_4882.mov Magnus On 10/29/2018 10:23 AM, Jörg wrote:
Before discussing the audio format you need a sound HW. Jörg
-----Original Message----- From: Oberon <oberon-bounces@lists.inf.ethz.ch> On Behalf Of Tomas Kral Sent: Monday, October 29, 2018 2:22 PM To: Oberon@lists.inf.ethz.ch Subject: [Oberon] FPGA - Oberon - Sound
Hi,
What could be a simple sound format for Oberon, possibly something better to PC Speaker or ZX Spectrum buzzer. It should be very conservative on memory use.
Did Ceres have some sound output? Many thanks.
-- Tomas Kral <thomas.kral@email.cz> -- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
-- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
Great. Didn't know. Thx Jörg -----Original Message----- From: Oberon <oberon-bounces@lists.inf.ethz.ch> On Behalf Of Magnus Karlsson Sent: Monday, October 29, 2018 6:57 PM To: oberon@lists.inf.ethz.ch Subject: **** SPAM **** [ 13.89 ] Re: [Oberon] FPGA - Oberon - Sound Pepino can do sound :) Yamaha OPL2 chip emulated in Verilog: http://www.saanlima.com/videos/IMG_4882.mov Magnus On 10/29/2018 10:23 AM, Jörg wrote:
Before discussing the audio format you need a sound HW. Jörg
-----Original Message----- From: Oberon <oberon-bounces@lists.inf.ethz.ch> On Behalf Of Tomas Kral Sent: Monday, October 29, 2018 2:22 PM To: Oberon@lists.inf.ethz.ch Subject: [Oberon] FPGA - Oberon - Sound
Hi,
What could be a simple sound format for Oberon, possibly something better to PC Speaker or ZX Spectrum buzzer. It should be very conservative on memory use.
Did Ceres have some sound output? Many thanks.
-- Tomas Kral <thomas.kral@email.cz> -- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
-- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
-- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
No, Atari ST used a simpler sound generator chip. See http://www.atkinsoft.com/soundgenerators.html On 10/29/2018 11:48 AM, Tomas Kral wrote:
On Mon, 29 Oct 2018 10:56:41 -0700 Magnus Karlsson <magnus@saanlima.com> wrote:
Yamaha OPL2 The very same YM, ATARI ST machine has?
need a sound HW.
Pepino LX9 supports audio, but how to map audio in `UCF' constraint file? How do I know what location corresponds to what hardware connected? Comparing `Pepino' wiring diagram with various `UCF' files I have got, I simply cannot see any clue, as also `UCF' files differ albeit for the same platform. e.g. One file #DIP switch NET "SWI[0]" LOC = "G14" | PULLDOWN; # right-most switch ... The other NET "swi[0]" LOC = "F12"; # no pull down? ... # SRAM NET "SRAM_CE0" LOC = "H4"; #active low ... The other # SRAM NET "SRce0" LOC = "P7"; How do I know the `LOC'ation? # audio NET "AudioL" LOC = "???"; NET "AudioR" LOC = "???"; -- Tomas Kral <thomas.kral@email.cz>
The generic Pepino .ucf file with all pins defined is available here: http://www.saanlima.com/download/pepino-v1.1/pepino.ucf The complete OPL2 project is available here: http://www.saanlima.com/download/pepino-v1.1/opl2_pepino_lx9.zip For sound you need to implement a simple 1-bit DAC, also called sigma-delta DAC. It basically produce a digital waveform with the high/low ratio equal to the input analog value. Here is the dac module used in the OPL2 project. It takes a 12-bit analog value and produce a 1-bit digital waveform with high/low ratio based on the analog value: module dac(clock, DACin, DACout); input clock; input [11:0] DACin; output DACout; reg [12:0] accumulator; always @(posedge clock) accumulator <= accumulator[11:0] + DACin; assign DACout = accumulator[12]; endmodule On 10/29/2018 12:03 PM, Tomas Kral wrote:
need a sound HW. Pepino LX9 supports audio, but how to map audio in `UCF' constraint file?
How do I know what location corresponds to what hardware connected?
Comparing `Pepino' wiring diagram with various `UCF' files I have got, I simply cannot see any clue, as also `UCF' files differ albeit for the same platform.
e.g.
One file #DIP switch NET "SWI[0]" LOC = "G14" | PULLDOWN; # right-most switch ... The other NET "swi[0]" LOC = "F12"; # no pull down? ... # SRAM NET "SRAM_CE0" LOC = "H4"; #active low ... The other # SRAM NET "SRce0" LOC = "P7";
How do I know the `LOC'ation?
# audio NET "AudioL" LOC = "???"; NET "AudioR" LOC = "???";
At the top level you need to add two output signals called AUDIO_L and AUDIO_R. You need to instantiate two dac units, one for left and one for right and hook them up like this: dac left_dac( .DACout(AUDIO_L), .DACin(analog_left), .clock(clk) ); dac right_dac( .DACout(AUDIO_R), .DACin(analog_right), .clock(clk) ); where analog_left and analog_right are the 12-bit analog values to convert. Magnus On 10/29/2018 1:48 PM, Tomas Kral wrote:
On Mon, 29 Oct 2018 21:20:05 +0100 Tomas Kral <thomas.kral@email.cz> wrote:
How do I connect `DACout' to
# audio NET "AUDIO_L" LOC = "K15"; NET "AUDIO_R" LOC = "K16";
in `Pepino_UCF'? like this ???? assign AUDIO_L = DACout; just left channel
On Mon, 29 Oct 2018 14:07:25 -0700 Magnus Karlsson <magnus@saanlima.com> wrote:
where analog_left and analog_right are the 12-bit analog values to convert.
Thank you, perhaps `analog_left/right' can be mapped at I/O port to a H/W address register. (iowadr == 23) ? {24'b0, dataKbd} : // -36 ... (iowadr == 26) ? {8'b0, analog_left, analog_right} : 0); // -24 ???? -- Tomas Kral <thomas.kral@email.cz>
It's a bit more complicated that that. You need to have something that generates the analog values at the analog sample rate you want to use. I have another project called waveplayer for the LX25 version of Pepino that will play wave files (like song.wav) stored on an sd-card. The wave file header contains information about the wave file, like stereo or mono, sample size in bits and sample rate (like 44.1 kHz). In hardware I have a 32-bit FIFO that holds up to 1024 analog samples (2 * 16-bit). The FIFO is written by the CPU as long as the FIFO has room for more data, until the song is done. The FIFO is read by hardware at a programmable rate, i.e. there is a timer in hardware that controls the rate that the values in the FIFO are read and fed to the dacs. The timer is programmed according to the sample rate (i.e. at 44.1 kHz the time between each read is 1/44100 sec). The waveplayer project is available here: http://www.saanlima.com/download/pepino-v1.1/waveplayer.zip Magnus On 10/29/2018 2:16 PM, Tomas Kral wrote:
On Mon, 29 Oct 2018 14:07:25 -0700 Magnus Karlsson <magnus@saanlima.com> wrote:
where analog_left and analog_right are the 12-bit analog values to convert. Thank you, perhaps `analog_left/right' can be mapped at I/O port to a H/W address register.
(iowadr == 23) ? {24'b0, dataKbd} : // -36 ... (iowadr == 26) ? {8'b0, analog_left, analog_right} : 0); // -24 ????
On Mon, 29 Oct 2018 14:27:39 -0700 Magnus Karlsson <magnus@saanlima.com> wrote:
You need to have something that generates the analog values at the analog sample rate you want to use.
Let's go simple first, I wish to do sampling in S/W to achieve something like ZX Spectrum did with 1-bit beeper sound. I will go for short beeps, while beeping, nothing else is executed. A beeper of 20-25mW plugged right into the Pepino jack socket, no amplifier, possible? That's only one channel, the other channel I was hoping to do the reverse. A/D conversion in Verilog, say a simple termistor circuit plugged in to the Pepino jack socket, to sense ambient temperature, Oberon then showing some trends in time. Possible? -- Tomas Kral <thomas.kral@email.cz>
On Mon, 29 Oct 2018 21:20:05 +0100 Tomas Kral <thomas.kral@email.cz> wrote:
How do I connect `DACout' to
# audio NET "AUDIO_L" LOC = "K15"; NET "AUDIO_R" LOC = "K16";
in `Pepino_UCF'?
Ah, probably need to instantiate from the top module first with clock. DAC (.clk(clk), ...?) ... assign assign AUDIO_L = DACout; But I need to also map I/O to DACin, somehow, right? assign inbus = ~ioenb ? inbus0 : ((iowadr == ??) ?? : -- Tomas Kral <thomas.kral@email.cz>
participants (3)
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Jörg -
Magnus Karlsson -
Tomas Kral