July 2018 - Oberon - mailman3.inf.ethz.ch

Re (2): Re (2): Explaining Texts.
by peter＠easthope.ca 28 Jul '18

28 Jul '18

From: =?UTF-8?B?SsO2cmc=?= <joerg.straube(a)iaeth.ch> Date: Sat, 28 Jul 2018 08:50:10 +0200 > Here an example: > > - Texts.Text represents this string ... Good. "org" and "pce" can't be understood properly without understanding operation of the cache. Will work on the Oberon Texts section again in a few days. Thanks, ... Lyall E. -- Message composed and transmitted by software designed to avoid the need, overhead and vulnerability of antivirus software. 123456789 123456789 123456789 123456789 123456789 123456789 123456789 Tel: +1 360 639 0202 http://easthope.ca/Peter.html Bcc: peter at easthope. ca

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Moving oberon to RISCV?
by Travis Ayres 28 Jul '18

28 Jul '18

I realize this is a lot of work, but there's quite a bit of momentum for RISCV. What would need to be done to port Oberon?

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Re: [Oberon] Re (2): Explaining Texts.
by Josef Templ 28 Jul '18

28 Jul '18

if I remember correctly, you should not think of the text pieces as in memory text blocks but as references to text stretches on files. A piece is always on a file and has a start pos and a length. The length can exceed the main memory. Only a part of the file will be kept in memory, depending on the buffering strategy in module Files. This allows, in principle, editing texts that are larger than the main memory. It also allows for a lot of sharing. If you copy a text then the piece list will be copied but the pieces will refer to the same file and position. The pieces are treated read-only for that. It also allows to open texts quickly because not all of the contents will be read into main memory. - Josef

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Re: [Oberon] Oberon board availability
by Chris Burrows 28 Jul '18

28 Jul '18

That's very interesting. Is that on the Pepino LX9 or the LX25? Is your Verilog code and Oberon code (assuming you mean you now have a 16-colour version of RISC5 Project Oberon) publicly available? Regards, Chris Burrows CFB Software http://www.astrobe.com/RISC5 > -----Original Message----- > From: Jörg [mailto:joerg.straube@iaeth.ch] > Sent: Saturday, 28 July 2018 4:32 PM > To: chris(a)cfbsoftware.com; ETH Oberon and related systems > Subject: Re: [Oberon] Oberon board availability (was Moving oberon to > RISCV?) > > Just a side note: > > I implemented 16 colors on the Pepino and did the Verliog change on a > Mac bootcamped in Windows 10. > > br > > J�rg >

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Re (2): Explaining Texts.
by peter＠easthope.ca 28 Jul '18

28 Jul '18

From: =?UTF-8?B?SsO2cmc=?= <joerg.straube(a)iaeth.ch> Date: Thu, 26 Jul 2018 08:53:12 +0200 > BTW: the two fields "pce" and "org" are not "pointers in a translation > cache", they are the cache. Is this any better? (Elliminate the preposition. "translation cache" becomes attributive to piece.) org: Offset in characters[0,len) of translation cache piece. Regards, ... Lyall E. -- Message composed and transmitted by software designed to avoid the need, overhead and vulnerability of antivirus software. 123456789 123456789 123456789 123456789 123456789 123456789 123456789 Tel: +1 360 639 0202 http://easthope.ca/Peter.html Bcc: peter at easthope. ca

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Syntax Diagrams
by Chris Burrows 27 Jul '18

27 Jul '18

> From: Oberon [mailto:oberon-bounces@lists.inf.ethz.ch] On Behalf Of > eas lab > Sent: Saturday, 28 July 2018 5:35 AM > To: ETH Oberon and related systems > Subject: Re: [Oberon] Moving oberon to RISCV? > > Who remembers the <railway diagrams> representation of syntax-tables? > The diagrams where stretched-out to show 1-node per line. > Then train <jumped> to the <action> as it passed the corresponding > node/station. I remember them. I found the 'railroad' syntax diagrams very helpful when using CDC Pascal at work in the 1970's. They made the recursive nature of Pascal's type system (an exciting new concept to me with my prior FORTRAN experience) so easy to understand. Here are the latest Oberon equivalents: http://www.astrobe.com/OberonSyntax/html/OberonSyntax.htm The diagrams were generated using 'EBNF Visualiser' which you can download from: http://dotnet.jku.at/applications/Visualizer/index.html You just feed it the EBNF text definitions and it creates the diagrams for you. Regards, Chris Burrows CFB Software http://www.astrobe.com

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Re: [Oberon] Explaining Texts.
by Jörg 27 Jul '18

27 Jul '18

Peter E. If you implemented Text as ONE contiguous block in memory, then you would have to move a lot of memory around if you insert or delete text. To overcome this: We introduce the idea of piece; a piece is a contiguous block of text (characters) in memory. A Text is a list of pieces. So, if you read-in an ASCII text from a file, the Text consist (in the beginning) of only ONE piece; all the ASCII characters are contiguous in memory and represented by one piece. Now, if you eg delete char 300 to 309 of that text, this one starting piece is spilt in two: first piece points to characters 1..299 the other piece points to 310..end. So, you deleted 10 characters without moving any memory around. BTW: the two fields "pce" and "org" are not "pointers in a translation cache", they are the cache. This cache is a minor implementation detail (optimization) of "FindPiece" and not so important to understand the idea. When you want to find the 3256th character in the Text, you basically have to go through all pieces in the list one by one and add up the piece's length until the sum is larger than 3256. Then you found the piece, where the 3256th character is in. As it is very often the case that you move the cursor back and forth or up and down, it is handy not do the whole piece length summation again and again. So, Text has a cache of the last found position (org = 3256, and pce is the piece, where postion "org" is in). If you search for the piece where the 3260th character is in, you start from this cache instead from position 0 again. br Jörg Am 26.07.18, 07:57 schrieb "Jörg" <joerg.straube(a)iaeth.ch>: Peter E. You have a "strange" approach: On one hand you want to understand high level things like concepts and abstractions and on the other hand you go down to low level things like memory used. In my whole career I was only interested in the nbr of bytes and internal element memory alignment rules when I wrote compilers. In my point of view, it's not too useful to understand Texts when you know how much memory a Piece occupies. This memory thingy heavily depends on the compiler not on the language and not on the module you want to understand. BTW: you always can find the nbr of bytes used by a type T by using size := SYSTEM.SIZE(T); Before going down to this detail, it is more important to understand this model: https://en.wikipedia.org/wiki/Model–view–controller This basic mechanism of separating data from user interface is used by Texts (data model) and TextFrames (user interface). And you should read this documentation: https://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.System.pdf - Figure 2.2 gives you an view on how the kernel modules are layered. - Chapter 5 explains Texts and its piece editor in detail. br Jörg Am 26.07.18, 06:44 schrieb "oberon-bounces(a)lists.inf.ethz.ch im Auftrag von peter(a)easthope.ca" <oberon-bounces(a)lists.inf.ethz.ch im Auftrag von peter(a)easthope.ca>: Hi, For me, one the bigger difficulties in understanding the system is from the multiple layers of abstraction. An intention in https://en.wikibooks.org/wiki/Oberon#Oberon_Text is to encapsulate abstractions concisely together. Understanding the relationship of an abstraction to something concrete can also help. Hence the "Memory Occupied" column in the tables. Is that information helpful or distracting or misleading? Thanks, ... Peter E. -- Message composed and transmitted by software designed to avoid the need, overhead and vulnerability of antivirus software. 123456789 123456789 123456789 123456789 123456789 123456789 123456789 Tel: +1 360 639 0202 http://easthope.ca/Peter.html Bcc: peter at easthope. ca -- Oberon(a)lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon

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Re: [Oberon] Arduino MKR Vidor 4000 (was New Hardware for Oberon / Risc-5 ?)
by Skulski, Wojciech 27 Jul '18

27 Jul '18

Markus: > they write ___SRAM___ > It comes loaded with hardware and potential: an 8 MB _____SRAM_____; It depends, where they write it. "This board hosts a number of features: onboard 8 Mbyte SDRAM". www.arduino.cc/en/Guide/MKRVidor4000 I took the photo of the board (www.arduino.cc/en/Guide/MKRVidor4000#toc10) magnified with IrfanView, sharpened the image (it was blurry), and I could read the chip part number which starts with "AS4C". I typed AS4C into DigiKey search, and a list of Alliance Memory parts came up. All of these are SDRAM chips of various kinds. > Thats the reason why I was so elctrified about this product. > But I fear its a typo, SRAM would be quite unusual. It is SDRAM. 8 megs of SRAM would take more space. > Have seen a schematic anywhere? I can't found it. The information density of their web is pretty low. The ratio of advertising blurb to true information is high. It is one more of these "look how easy the computer programming is you do not need to know much just type in a few commands...". Their FPGA programming tutorial is somewhat sketchy. If you want to learn FPGA then you need to buy Pong Chu books and read them. A couple web pages will not do. The board itself may be OK, but look at the interfaces. The general purpose ones are a small bunch of 0.1" pins. Good for driving LEDs, pushbuttons, PWM, etc. Not good for any performance apps. Just my 2 cents. Wojtek

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Moving oberon to RISCV?
by Andreas Pirklbauer 27 Jul '18

27 Jul '18

> I realize [Moving oberon to RISC[-]V] is a lot of work, > but there's quite a bit of momentum for it. > What would need to be done to port Oberon? In essence, you would need to do two things: 1. Find a suitable hardware board that supports the RISC-V instruction set architecture (http://riscv.org) or use an emulator with RISC-V support such as QEMU (http://github.com/riscv/riscv-qemu) 2. Change the code generator of the Oberon compiler to generate instructions for the RISC-V CPU (see also http://oberon.wikidot.com/oberon-linux-revival-olr) If you want to port the entire Oberon system, you mayalso need to adapt some inner and outer core modules(e.g., Kernel, Display), depending on the HW you use. It would set you back 1-3 months, assuming familiaritywith both the RISC-V processor architecture and theOberon compiler, in particular its code generator. -ap

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New Hardware for Oberon / Risc-5 ?
by greim 27 Jul '18

27 Jul '18

Hello, Arduinio brought a brand new FPGA board to the market! Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM https://store.arduino.cc/arduino-vidor-4000 Not much info yet. Seems they will build the future software on System Verilog. And maybe they create also a Verilog dev. platform on the web. Could imagine that Intel will support it. Their standing in the embedded world is friendly spoken quite weak up to now. But Arduinio was a success story up to now, so I am optimistic that they will bring FPGA programming to the people, as they did with microcontroller programming. Could any body say if the Cyclone 10CL016 is powerful enough to handle the Oberon system? Bringing Oberon and Arduinio together would be a big step ahead for Oberon / Risc-5, I think. Markus

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