- Oberon - mailman3.inf.ethz.ch

V4 folds.
by peter＠easthope.ca 07 Aug '21

07 Aug '21

I've added "fold" in https://en.wikibooks.org/wiki/Oberon#Glossary . Comments? A better explanation? Thx, ... P.L. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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Keyboard input in ETH Oberon.
by peter＠easthope.ca 05 Aug '21

05 Aug '21

Hi, ETH Oberon Input.Mod of is visible in the screenshot at http://easthope.ca/ETHO.Input.Mod.png . The Oberon is running on QEMU on Linux Debian. In the upper viewer, ET shows some of the source for the keyboard translation table. Below that Hex shows the content beginning with Oberon accents. Questions (1) What is achieved by "POP EAX ... RET"? (2) What is DB? (3) The syntax is explained as, table = { scancode unshifted-code shifted-code flags } 0FFX . Therefore scan code 1EX represents "a"; 1EX + shift represents "A"? (4) 4X represents bit 04, flag 2? Caps Lock effect? (5) The first two characters under "Oberon accents" appear to be auml and Auml. Hex shows 83 and 80 whereas the ASCII Latin-1 Supplement encodes auml and Auml as E4 and C4. How does that work? (6) Why is 0FFX necessary? Thx, ... P.L. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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Re (2): Keyboard input in ETH Oberon.
by peter＠easthope.ca 04 Aug '21

04 Aug '21

Hellwig and Jörg, Thanks for your replies. With fog dispersed, the mountainous scenery is pleasant. =8~) Incorporating your explanations into the wikibook. Criticisms always welcome. From: Hellwig Geisse <hellwig.geisse(a)mni.thm.de> Date: Wed, 4 Aug 2021 11:57:31 +0200 > CALL L1 (with the label L1 directly following the call) pushes > the return address onto the stack, in this case the numerical > value of L1. In the Talk page associated with the module page, I've added comments with links. Module page https://en.wikibooks.org/wiki/Oberon/ETH_Oberon/2003-01-05/Input.Mod Talk page https://en.wikibooks.org/wiki/Talk:Oberon/ETH_Oberon/2003-01-05/Input.Mod > [DB] The assembler directive to deposit the following bytes into > memory. Haven't found a good explanation of that in https://en.wikibooks.org/wiki/X86_Assembly/ . It is rated only half finished. DB may be something to add. From: =?UTF-8?B?SsO2cmc=?= <joerg.straube(a)iaeth.ch> Date: Wed, 4 Aug 2021 12:33:55 +0200 > The 80X and 83X are the Oberon coding of Auml and auml. Has nothing > to do with ASCII or Latin-1 or Unicode. It's Oberon coding used by the > Oberon font engine. Characters above 127X are not in https://en.wikibooks.org/wiki/Oberon/ETH_Oberon/2003-01-05/Input.Mod yet. Will fix that. Ideally the translation should be handled automatically in MediaWiki.Mod. (When I think MediaWiki.Mod is finished another deficiency appears.) Thanks again, ... P. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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testmail
by Felix Friedrich 04 Aug '21

04 Aug '21

This is a testmail that can safely be ignored.

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A new dialect? Oberon+ (OBX)
by Liam Proven 29 Jul '21

29 Jul '21

https://oberon-lang.github.io/ -- Sent from my smartphone. Please pardon brevity & typos.

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Re (2): Copy or reinstall A2?
by peter＠easthope.ca 27 Jul '21

27 Jul '21

From: Liam Proven <lproven(a)gmail.com> Date: Mon, 19 Jul 2021 09:54:12 +0200 > Doesn't anyone run A2 directly on x86? I Have but LinuxA2 is convenient & flexible. A Linux machine and an A2 machine can be networked. Otherwise have the two systems on one machine. Linux with LinuxA2, Windows with WinA2, etc. Did you see my 2nd reply? http://lists.inf.ethz.ch/pipermail/oberon/2021/015968.html Incidentally, the Fox compiler in A2 is a cross compiler. A relatively small investment of making a back end for the RISC machine would allow Fox to produce RISC object code. Regards, ... P.L. -- 48.7693 N, 123.3053 W tel: +1 604 670 0140

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Re: [Oberon] ARM Varieties (was: Copy or reinstall A2?)
by Chris Burrows 26 Jul '21

26 Jul '21

> -----Original Message----- > From: Oberon [mailto:oberon-bounces@lists.inf.ethz.ch] On Behalf Of > Liam Proven > Sent: Thursday, 22 July 2021 12:38 AM > To: ETH Oberon and related systems > Subject: Re: [Oberon] Re (2): Copy or reinstall A2? > > > Incidentally, the Fox compiler in A2 is a cross compiler. A > > relatively small investment of making a back end for the RISC > > machine would allow Fox to produce RISC object code. > > Which particular RISC machine do you have in mind? > I assumed by saying *the* RISC machine to this audience he meant Wirth's RISC5. However, if that is so, I would not categorise the task as a 'relatively small investment'. > I was aware of this, yes, and I was considering trying to produce an > experimental ARM executable and seeing if I could run it on a Raspberry Pi. > I know it will not have any I/O without drivers for USB etc., but > maybe if I could get as far as writing something to the screen, that would be progress. > Good luck with that! The ARM company have designed a wide range of different architectures with varying degrees of (in)compatibility. https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures AFAICS the ARM compiler in A2 targets the StrongArm architecture developed by DEC in the 1990s which belongs to the ARM8 family. ARM architectures used by the various versions of Raspberry Pi include ARM11, Cortex-A7, Cortex-A53 and Cortex-A72 Regards, Chris Burrows CFB Software https://www.astrobe.com

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Re (2): Re (2): Accessibility of FPGA configuration to V5 system.
by peter＠easthope.ca 26 Jul '21

26 Jul '21

From: Michael Schierl <schierlm(a)gmx.de> Date: Sat, 24 Jul 2021 19:29:45 +0200 > It would be possible to build a RISC machine that can change while the > OS is running. The current version does not provide that capability. Very helpful clarification. Thanks. The idea of changing the machine during operation seemed relevant to a specific problem. Probably better to address entirely in software. The problem isn't Oberon specific but if there is an interest I can explain more. From: "Skulski, Wojciech" <skulski(a)pas.rochester.edu> Date: Sat, 24 Jul 2021 18:53:47 +0000 > ... first spend a couple weeks reading the official FPGA data sheets > and User Guides for different aspects of the FPGA, followed by a few > weeks of reading the vendors' fora, ... Appealing and I don't doubt the value but Andr Fischer has given permission to put his Oberon Tutorial in the wikibook and that is my current effort. Regards, ... P.L. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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Re (2): Accessibility of FPGA configuration to V5 system.
by peter＠easthope.ca 24 Jul '21

24 Jul '21

From: Michael Schierl <schierlm(a)gmx.de> Date: Sat, 24 Jul 2021 15:21:45 +0200 > The V5 system treats the RISC5 processor as a black box. It is not > aware whether it is implemented as FPGA, as an ASIC or an emulator. Understood. Although obviously I would have to learn far more to re-implement on a new FPGA or to make another emulator and etc. > While there is LOLA, it will only output Verilog and there are no > tools in V5 to compile these to a bitstream of any FPGA model. A limitation of software implementation. (?) > Also, the processor does not expose any way of altering (parts of) the > bitstream it is running from. In other words, the host RISC machine can not change while the OS is running? At the fundamental level, a gate in the array is in one of two states. The state of a gate can't be switched while the system is running? How is that prevented? Thx, ... P.L. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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Accessibility of FPGA configuration to V5 system.
by peter＠easthope.ca 24 Jul '21

24 Jul '21

Hi, Can the V5 system ascertain the configuration of the host FPGA? Can the V5 system change the configuration of the host FPGA? Thx, ... P.L. -- 48.7693 N 123.3053 W tel: +1 604 670 0140

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